A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Deposition of a thinner conductive film which thoroughly covers the bottom and comer of small-geometry openings in integrated circuits is becoming critical for scaling down of IC dimensions. A recent need for thin conductive films is for a barrier layer between copper interconnect and insulating material. In metallization for interconnects, as the dimension of metal lines are scaled down, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
However, copper is a mid-bandgap impurity in silicon. Furthermore, the presence of copper in an insulating layer may also degrade the insulating properties of the insulating layer. Thus, diffusion of copper into an active device area in silicon or an insulating layer may degrade the performance of the integrated circuit. Nevertheless, use of copper metallization is desirable for further scaling down integrated circuit dimensions because of the lower bulk resistivity and the higher electromigration tolerance of copper.
Thus, a conductive film is deposited as a barrier layer between copper and the insulating layer to impede diffusion of copper into the insulating layer. As integrated circuit dimensions are scaled down, a thinner barrier layer is desirable.
The present invention is described with depositing conductive material to fill a dual damascene opening having a trench line and a via hole for integrated circuit interconnect metallization. However, as would be apparent to one of ordinary skill in the art, the present invention may be used for depositing conductive material for any application within an integrated circuit.
As an integrated circuit is scaled down, metallization, which connects devices on the integrated circuit, is also scaled down. Metal lines having copper for scaled-down integrated circuits are fabricated using a damascene process. A trench line or a via hole or any other opening is filled with metal or any other conductive material. For damascene metallization openings, the surface of the integrated circuit is then polished to form conductive lines with the conductive material contained within the trench lines.
Referring to FIG. 1, integrated circuits typically include multi-level metallization, and FIG. 1 shows a cross-section of a multi-level dual damascene metallization opening having a trench line and a via hole for integrated circuit metallization. A first metal line is contained within a first trench opening 102 etched in a first trench insulating layer 103 deposited on a substrate layer 104. A second metal line is contained within a second trench opening 105 in a second trench insulating layer 106. The second metal line is disposed on a different metallization level from the first metal line.
A via interconnects the metal lines on the two different metallization levels. A via plug is comprised of a conductive material and is disposed within a via hole 108 etched in a via insulating layer 110. FIG. 2 shows a top view of the dual damascene opening of FIG. 1, with the dual damascene cross-section of FIG. 1 being across line AA of FIG. 2.
The insulating layers 106 and 110 are comprised of any insulating material such as any form of oxides as is known to one of ordinary skill in the art. The conductive material filling the trench line 105 and the via hole 108 is commonly copper for scaled-down integrated circuits. To prevent diffusion of copper into the surrounding insulating layer, a barrier layer 112 comprised of a conductive film is deposited between the copper and the insulating layers 106 and 110. (Note, the first metal line within the first trench opening 102 may also be copper. In that case, a barrier layer is deposited between the first metal line and the first trench insulating layer 103. Such a barrier layer is not shown in FIG. 1 for clarity of illustration.)
As integrated circuits are scaled down, a process for easily and economically depositing conductive material, including a thin conductive film for the barrier layer 112 and the copper fill within the trench opening 105 and the via hole 108 having small dimensions, is desired. Prior art methods for depositing such conductive material include physical vapor deposition (PVD) and chemical vapor deposition (CVD) as known to one of ordinary skill in the art of integrated circuit fabrication. However, such prior art methods do not fully deposit conductive material into the bottom and comers of small-geometry openings. In addition, CVD techniques sometimes require high processing temperature and high-cost chemical ingredients, and CVD techniques sometimes result in high resistivity compound formation.